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[Other resource] State.Machine

Description: State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
Platform: | Size: 124507 | Author: 咱航 | Hits:

[Other resource] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113973 | Author: mingming | Hits:

[Other] FSM_DESIGN

Description: 非常好的FSM设计，对于学习VHDL的人有很好的参考价值。-very good design, VHDL for the study of a very good reference value.
Platform: | Size: 571522 | Author: zhangbijun | Hits:

[VHDL-FPGA-Verilog] control_fsm_rtl.vhd

Description: ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机-ALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSM
Platform: | Size: 7168 | Author: 王俊龙 | Hits:

[VHDL-FPGA-Verilog] rafal2

Description: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Platform: | Size: 941056 | Author: nukom | Hits:

[Software Engineering] spi

Description: send SPI data that is writen as FSM-send SPI data that is writen as FSM
Platform: | Size: 1024 | Author: rez | Hits:

[VHDL-FPGA-Verilog] quicklogicuart

Description: Uart vhdl design FSM
Platform: | Size: 214016 | Author: like | Hits:

[VHDL-FPGA-Verilog] CM12864

Description: cm12864液晶显示器的vhdl驱动代码，基于状态机的转换，实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.
Platform: | Size: 1024 | Author: 梁重 | Hits:

[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte

Description: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Platform: | Size: 5072896 | Author: mabeibei | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[VHDL-FPGA-Verilog] coder_counter

Description: 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] fsm

Description: VHDL新手入门：有限状态机练习（三段式结构）-VHDL Getting Started: Finite state machine exercises (three-stage structure)
Platform: | Size: 1024 | Author: Domo | Hits:

[VHDL-FPGA-Verilog] AD7938controllor-VHDL

Description: VHDL语言的有限状态机法控制8位/12位自动转换通道模数转换器AD7938-VHDL, FSM method to control 8-bit/12-bit ADC AD7938 auto-conversion channel
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] fsm

Description: truong trinh mau cho viet fsm cu vhdl
Platform: | Size: 1024 | Author: hung | Hits:

[Other] fsm

Description: finite state machine writing in VHDL using proteus software.
Platform: | Size: 13312 | Author: saltihie | Hits:

[VHDL-FPGA-Verilog] FSM

Description: 关于状态机的规范编码风格，有具体的verilog，vhdl实例-On the norms of the state machine coding style, specific Verilog, VHDL instance
Platform: | Size: 83968 | Author: charley | Hits:

[VHDL-FPGA-Verilog] fsm

Description: 检测连续3个1的状态机的VHDL代码，输入11111则输出00111，ISE可以编译仿真，运行-Detecting consecutive three one state machine VHDL code, enter 11111 Output 00111, ISE can compile simulation run
Platform: | Size: 340992 | Author: 林恩 | Hits:

[assembly language] FSM

Description: 这是用 vhdl所实现的有限状态机的代码，是学VHDL的基本-this is the VHDL for finite state machine.
Platform: | Size: 1024 | Author: lilyhe | Hits:

[Industry research] 3.-VHDL-Design-of-FSM

Description: This consists of very basics of VHDL programming for FSM.
Platform: | Size: 401408 | Author: Parikshit | Hits:

[Other] LAB

Description: SAM VHDL编码，包括数据选择器，加法器，简易逻辑电路，有限状态机等(FSM SAM ALU and many other different parts)
Platform: | Size: 6144 | Author: TimeParaodgs | Hits:
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